Single clock edge triggered synchronous integrated circuits are circuits in which sequential elements in the integrated circuit operate at either the rising or falling edge of the clock. The edge on which the sequential elements operate is known as the operable edge. For example, the elements may carry out an operation on a rising edge of a clock while the falling edge of the clock resets the clock signal so that another rising edge can occur. The sequential elements may be elements such as flip-flops and/or memories.
Propagation of each clock edge through a clock tree dissipates power. The power dissipation may be due to, for example, the switching of logic devices and corresponding capacitance. In some single clock edge triggered systems, the power consumed per operation may include the power dissipated by the propagation of the rising clock edge and the power dissipated by the propagation of the falling clock edge.
Dual edge clocked systems may provide power per operation savings. Memories for such a system have been suggested with an inclusion of an external edge detector on the system clock path. Alternatively, a memory for a dual edge clocked system may be triggered by a rising or falling edge (as required) of a dedicated memory clock signal generated from the system clock at double the system clock frequency. However, the introduction of external edge detectors adds a power and performance penalty, partly nullifying the power gained by virtue of dual edge operation, while the implementation of two clock trees may be complex because of requirement to balance two different clock trees.